1. Technical Field
Various embodiments relate generally to an electronic device.
2. Related Art
A semiconductor includes a cell array storing data and a plurality of circuits configured to perform program, erase and read operations. Since the cell array includes a plurality of memory blocks, it is required to select one of the memory blocks for the program, erase or read operations with respect to the selected memory block. For this purpose, a semiconductor device includes a row decoder configured to select a memory block according to an address.
FIG. 1 is a block diagram illustrating a conventional semiconductor device.
Referring to FIG. 1, the semiconductor device includes the cell array including first to nth memory blocks and the row decoder configured to select one of the memory blocks according to row addresses XA, XB, XC and XD.
The row decoder includes first to nth high voltage generating circuits and first to nth pass transistor groups. The numbers of the high voltage generating circuits, the pass transistor groups and the memory blocks are the same as one another. For example, when the 4-byte row addresses XA, XB, XC and XD are input to each of the high voltage generating circuits, one of the high voltage generating circuits generates corresponding one of high voltage block selection voltages BLK1 to BLKn according to the row addresses XA, XB, XC and XD. A case where each address is 8 bits will be described as an example. Namely, XA is XA<8:1>, XB is XB<8:1>, XC is XC<8:1> and XD is XD<8:1>.
For an address of a memory block, one bit of the respective row addresses XA<8:1>, XB<8:1>, XC<8:1> and XD<8:1> becomes logic high, and the remaining seven bits of the respective row addresses become logic low. A memory block corresponding to the respective row addresses XA, XB, XC and XD, all of which have a logic high bit, is selected.
Each of the pass transistor groups includes a plurality of high voltage pass transistors coupled in common to global word lines GWL. The high voltage pass transistors included in each of the first to nth pass transistor groups are turned on by the block selection voltages and transmit the voltages from the global word lines GWL to local word lines LWL1 to LWLn.
For example, if the row addresses XA, KB, XC and XD input to the first high voltage generating circuit is ‘1111’, the first high voltage generating circuit generates the first high voltage block selection voltage BLK1. Since the row addresses input to the remaining high voltage generating circuits include at least one ‘0’ value, output nodes of the remaining high voltage generating circuits are either floated or discharged.
Meanwhile, since the conventional semiconductor device needs to include the voltage generating circuit and the pass transistor group for each of the memory blocks, there is a limit to downsize the semiconductor device. Particularly, the high voltage generating circuit, which includes a NAND gate configured to decode the row addresses and a plurality of switching devices, occupies a large area in the row decoder, and is one of serious factors of the limitation in downsizing.